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MyLogic Station



Digital Circuit Editor, Logic Simulator

MyLogic Station V5.1 is the schematic capture with logic-level simulator solution to provide easy to use and cost effective way of making prototypes. MyLogic Station V5.1 enables FPGA design by generating schematic netlist to structural VHDL or EDIF netlist. And it accepts VHDL codes or EDIF to generate the schematic data.

MyLogic Station™

  • SchEd_Analoog : Schematic / Symbol Editor

  • Logic2SPICE: Extracts Standard SPICE, HSPICE, PSPICE, CDL

  • MySPICE : Analog Circuit (SPICE) Simulator

  • MyPostProcessor: Graphical Simulation Analyzer


Main Features

  • SchEd : Schematic Editor : State Diagram Editor

    •   Supports on-line circuit check

    • Structural VHDL generation

    • Boolean Equation

    • Schematic generation from EDIF netlist

    • MState Diagram Editor

    • EDIF netlist generation


  • MySim : Logic Simulator

    •   Logic level simulator

    • Supports typing commands

    • Waveform Analyzer

    • Easy to draw waveform for stimulus

    • Test bench generation for VHDL simulation


  • Logic2EDIF : EDIF Netlist Generator

  • SchGen (EDIF2Logic) : Schematic Generator

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