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MyVHDL Station

MyVHDL.bmp

Introduction

VHDL Compiler & Simulator

MyVHDL Station V5.1 is a VHDL simulator providing the integrated working environment to develop the VHDL design. In this workspace you can create, edit, compile, simulate and debug. MyVHDL Station has many features to enhance your development of VHDL design.

MyVHDL Station™

  • MyVHDL : VHDL Code Editor, Compiler, Simulator

  • WaveForm Editor: Automatic Test Bench Generator

MyVHDL.bmp

Main Features

  • MyVHDL : VHDL Code Editor, Compiler, Simulator

    • Supports both IEEE 1076-1987 and 1076-1993 VHDL standard

    • Supports Text I/O Library

      • File Read/Write

      • Textio.vhd, Std_logic_textio.vhd

    • Provides VHDL Wizard, syntax coloring, and other features to edit a VHDL file easily

    • User Friendly GUI and Various Wizards

    • Provides various kinds of debugging information for efficient debugging

    • Provides Smart Compile of the file base

    • Allows you to perform operations using commands

 

  • WaveForm Editor: Automatic Test Bench Generator

    • Automatic Test-Bench generation from waveform.